1. Field of the Invention
The invention relates to lithography, and more particularly to a mask for defining a rectangular trench and a method of forming a vertical memory device with a rectangular trench by the mask to improve the threshold voltage of transistor shift and increase the alignment process window.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. Dynamic random access memory (DRAM) is such an important semiconductor device in the information and electronics industry.
Most DRAMs presently have one transistor and one capacitor in one DRAM cell. Under increased integration, it is needed to shrink the size of the memory cell so as to manufacture the DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure can reduce its occupation area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of DRAM of 64 megabits and above. Traditional DRAM with a plane transistor covers larger areas of the semiconductor substrate and cannot satisfy demands for high integration. Therefore, use of vertical transistors which can save space is a current trend in fabrication of memory cells.
When the size of the trench capacitor and the vertical transistor are shrunk due to high integration, the alignment between the active area and the deep trench becomes more important. Unfortunately, misalignment is difficult to avoid in subsequent process. Moreover, the mask used for lithography is subjected to optical limitation, such as optical proximity effect (OPE), increasing the difficulty of lithography. For example, when the light source passes through a desired trench pattern (rectangular trench pattern) on the mask onto the imaging layer, a rounding trench pattern (oval trench pattern) is formed in the imaging layer due to light diffraction.
FIG. 1 is a plane view of partial layout of the conventional mask for defining a trench pattern. The mask 10 includes rectangular transparent regions 10a to define deep trenches in a semiconductor substrate, such as a silicon wafer.
FIG. 2 is a plane view of the alignment between the active area and the trench in a semiconductor substrate. In FIG. 2, deep trenches are defined by the mask 10 shown in FIG. 1. Here, in order to simplify the diagram, only one deep trench 12 is shown. As mentioned above, OPE makes the trench 12 has an oval top view, but not a desired top view (rectangular). In addition, when the active area AA is formed, the active area AA is shifted (as the active area AA′) due to misalignment. The misalignment between the active area AA′ and the rounding trench 12 changes the overlapping area, shifting the threshold voltage of the vertical transistor (not shown) in the trench 12 and changing its electrical properties. That is, the alignment process window is narrowed. As a result, the yield of the memory devices is reduced. Moreover, the area of the oval trench 12 is smaller than the rectangular one, reducing the capacitor (not shown) below the vertical transistor in the trench 12.